Attending this course the student is expected:
• to familiarize himself / herself with the design choices (tradeoff between cost and performance) of computer architectures
• to learn the internal organization of a complex parallel CPU and to design the basic modules of a specific CPU
• to fully understand the optimization mechanisms of both complex parallel processing systems and their hierarchical memories
Course Content (Syllabus)
• Computer System performance. Metrics.
• Design principles of RISC and CISC CPUs
• Hardwired and Microprogrammed Control Units
• Pipelined processors. Structural, Data and Control Hazards
• Branch prediction techniques.
• ISA parallelism. VLIW and superscalar architectures. Dynamic instruction scheduling
• Associative and Cache Memory architecture
• Virtual memory architecture
• Simulation (or /and FPGA implementation) of the Control Unit, Register Set and Arithmetic and Logic Unit (ALU)
Course Bibliography (Eudoxus)
Patterson D.A, και Hennessy J.L., "Αρχιτεκτονική υπολογιστών - Μια ποσοτική προσέγγιση", Έκτη Αμερικανική Έκδοση, Εκδόσεις Κλειδάριθμος, 2020