Low-level HW Digital Systems II

Course Information
TitleΨηφιακά Συστήματα HW σε Χαμηλά Επίπεδα Λογικής II / Low-level HW Digital Systems II
SchoolElectrical and Computer Engineering
Cycle / Level1st / Undergraduate
Teaching PeriodSpring
CoordinatorVasileios Pavlidis
Course ID600001042

Programme of Study: Electrical and Computer Engineering

Registered students: 55
OrientationAttendance TypeSemesterYearECTS
ELECTRICAL ENERGYElective Courses845

Class Information
Academic Year2021 – 2022
Class PeriodSpring
Instructors from Other Categories
Weekly Hours4
Class ID
Course Type 2016-2020
  • Scientific Area
Course Type 2011-2015
Specific Foundation / Core
Mode of Delivery
  • Face to face
Language of Instruction
  • Greek (Instruction, Examination)
General Prerequisites
1. The course unit of "Logic Design" 2. The course unit of "Low-level HW Digital Systems part I".
Learning Outcomes
1. Learning of design principles for digital sequential circuits 2. Learning and application of design methodology for Finite State Machines (FSMs) 3. Understanding of synchronization techniques for asynchronous signals and multiple clock domains 4. Learning of the hardware description language - Verilog and its application for the design of digital circuits 5. Learning and applying functional simulation tools for verifying digital circuits
General Competences
  • Apply knowledge in practice
  • Retrieve, analyse and synthesise data and information, with the use of necessary technologies
  • Make decisions
  • Work autonomously
  • Design and manage projects
  • Appreciate diversity and multiculturality
  • Respect natural environment
  • Demonstrate social, professional and ethical commitment and sensitivity to gender issues
  • Be critical and self-critical
  • Advance free, creative and causative thinking
Course Content (Syllabus)
Analysis of sequential components (FF and latches), design principles of digital sequential circuits, analysis and mitigation of hazards in combinational circuits, design methodology of Finite State Machines (FSM) (Mealy and Moore machines), modeling and analysis of metastability, synchronization of asynchronous signals, synchronization circuits between different clock domains, analysis and design of FIFO memory. Introduction to Verilog HDL, description of sequential and combinational circuits, generation of stimuli vectors and test benches for verification, description of FSM with Verilog
Educational Material Types
  • Slide presentations
  • Video lectures
  • Book
Use of Information and Communication Technologies
Use of ICT
  • Use of ICT in Communication with Students
Course Organization
Laboratory Work351.2
Student Assessment
Written Examination (180 min)
Student Assessment methods
  • Written Exam with Multiple Choice Questions (Summative)
  • Written Exam with Problem Solving (Summative)
  • Report (Summative)
  • Labortatory Assignment (Summative)
Course Bibliography (Eudoxus)
Digital Integrated Circuit Design Using Verilog and System Verilog, Ronald Mehrer, ISBN: 978-0-12-408059-1, Newnes, Elsevier, 2015. Quick Start Guide to Verilog, Brock J. LaMeres, ISBN 978-3-030-10551-8, Springer, 2019, (DOI: https://doi.org/10.1007/978-3-030-10552-5).
Additional bibliography for study
Digital Design and Computer Architecture, David Money Harris and Sarah L. Harris, ISBN: 978-0-12-394424-5, Morgan Kaufmann, Elsevier, 2013 (DOI: https://doi.org/10.1016/C2011-0-04377-6). The Art of Hardware Architecture, Mohit Arora, ISBN: 978-1-4614-0396-8, Springer, 2012 (DOI 10.1007/978-1-4614-0397-5).
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