DIGITAL SYSTEMS
| Title | ΨΗΦΙΑΚΑ ΣΥΣΤΗΜΑΤΑ / DIGITAL SYSTEMS |
| Code | ΗΦΥ202 |
| Faculty | Sciences |
| School | Physics |
| Cycle / Level | 2nd / Postgraduate |
| Teaching Period | Spring |
| Coordinator | Konstantinos Siozios |
| Common | No |
| Status | Active |
| Course ID | 600016884 |
Programme of Study: Electronic Physics (Radioelectrology)
Registered students: 22
| Orientation | Attendance Type | Semester | Year | ECTS |
|---|---|---|---|---|
| KORMOS | Compulsory Course | 2 | 1 | 6 |
| Academic Year | 2022 – 2023 |
| Class Period | Spring |
| Faculty Instructors |
|
| Weekly Hours | 2 |
| Class ID | 600221015
|
Mode of Delivery
- Face to face
Digital Course Content
- e-Study Guide https://qa.auth.gr/en/class/1/600221015
- eLearning (Moodle): https://elearning.auth.gr/course/view.php?id=9982
Language of Instruction
- Greek (Instruction, Examination)
- English (Instruction, Examination)
Learning Outcomes
The objective of this course is to introduce students to the concepts of digital system design, design of processing and control units. Introduction to VHDL for design, simulate and synthesize digital systems.
General Competences
- Apply knowledge in practice
- Adapt to new situations
- Make decisions
- Work autonomously
- Work in teams
- Work in an international context
- Generate new research ideas
- Be critical and self-critical
- Advance free, creative and causative thinking
Course Content (Syllabus)
- Section 1 (4 hours): Data paths and control units of non-programmable systems, Register Transfer Level, Microoperations, Bus techniques, ASM diagrams, Hardwired control, Design of finite state machines with complex transition conditions, Microprogammed control, Timing issues and metastability in digital systems.
- Section 2 (4 hours): Data paths and control units of programmable systems, Register file, Arithmetic Logic Unit, Single cycle architecture, Multi cycle architecture, Control units of programmable systems, Performance increase techniques: pipeline, hazards.
- Section 3 (12 hours): VHDL design of digital systems, VHDL code structure, variable types, Finite State Machines, Operators and their properties, Sequential and concurrent digital design, signals and variables, Implementation of algorithmic state machines, synchronous and asynchronous design. Practical exercise with Xilinx Vivado to simulate and synthesize digital designs.
- Section 4 (4 hours): System design with VHDL, Package and components, Functions and procedures, VHDL design of representative digital designs, Testbenches to verify functional verification.
Educational Material Types
- Notes
- Slide presentations
- Interactive excersises
Use of Information and Communication Technologies
Use of ICT
- Use of ICT in Course Teaching
- Use of ICT in Laboratory Teaching
- Use of ICT in Communication with Students
- Use of ICT in Student Assessment
Course Organization
| Activities | Workload | ECTS | Individual | Teamwork | Erasmus |
|---|---|---|---|---|---|
| Lectures | 78 | 3.1 | |||
| Written assigments | 69 | 2.8 | |||
| Exams | 3 | 0.1 | |||
| Total | 150 | 6 |
Student Assessment
Description
Final exams (students have to submit also their practice exercises).
Student Assessment methods
- Written Exam with Multiple Choice Questions (Summative)
- Written Exam with Short Answer Questions (Formative)
- Written Assignment (Formative, Summative)
- Written Exam with Problem Solving (Summative)
Bibliography
Additional bibliography for study
1. Logic and Computer design fundamentals, Third and Fourth edition, M. Morris Mano, Charles R. Kime, Pearson International Edition, 2008
2. Σχεδιασμός κυκλωμάτων με τη VHDL, Volnei A. Pedroni, Εκδόσεις Κλειδάριθμος, 2007
3. RTL Hardware Design Using VHDL, Pong P. Chu, John Wiley & Sons, 2006
4. Advanced FPGA Design: Architecture, Implementation, and Optimization, Steve Kilts, John Wiley & Sons, 2007
5. The Designer’s Guide to VHDL, Third Edition, Peter J. Ashenden, Jim Lewis, Morgan Kaufmann, 2008
6. Digital Engineering Design: A Modern Approach, Richard F. Tinder, Prentice Hall, 1991
Last Update
09-12-2021
