Course Content (Syllabus)
● Historical reference. The Generic ASIC integrated circuits. The PAL, GAL, PLA and their programming. Example, design of traffic signal controller in one PAL device. Multiple Array Matrix MAM. Intel EPLD architectures (covering 100 TTL circuits in one chip) and Altera APPEX, FLEX and MAX. The impossibility of further PAL and EPLD extension. ● CPLD devices. Altera and Xilinx software for their programming. ● FPGA devices. Basic categories and architectures, the ALTERA and XILINX families. The LUT and CLB structures, the levels of programmable interconnections. The IEEE JTAG 11.49.x. standard for programming. Multi-layer and 3-D FPGAs (today's sizes 4 billion MOSFET/ FINFET transistors in 24 nm). ● Regi-ster-Transfer Level (RTL) Design and Hardware Description Languages HDL. ● VHDL lan-guage. Theory, syntax and example, the vhdl code for MIPS processor. ● Verilog and System Verilog languages. Theory, syntax and the previous example with MIPS processor. ● XILINX-ISE and ALTERA-Quartus software for programming and simulation of FPGA devices. ● Soft-ware Processors of FPGAs. NIOS II, ARM CORTEX A-1 and Α-9, MP32 (MIPS). The architectu-res of Xilinx ZYNQ και Altera Aria families. ● Design from Higher Levels of Abstraction. Mo-del Based Design. Algorithms in C/C++. The Matlab - Simulink environment. Mixed analog / digital architectures, automatic transformation of C/C++ code onto vhdl and verilog. Coope-ration of Matlab with Xilinx and ALTERA software. ● HW/SW Co-design starting from high-level algorithms. ● Additional issues. Low-Power FPGA design, multiple clock models, Fault testing and Verification of FPGAs, regression tests, area/speed trade-off.
Laboratory works: 1. Design and programming a CPLD device. 2. Programming FPGA devi-ce by IEEE JTAG 11.49.x standard. 3,4. FPGA project design and programming by Xilinx-ISE and ALTERA Quartus software. 5. Embedding into an FPGA device, by using Matlab-Simu-link, of an adaptive VGA controller, installed into a car, and compensating vibrations descen-ding from the road irregularity. 6. Measurements and works with an educational bench mo-bile phone, through the development board ALTERA - Aria.