TECHNOLOGY OF SEMICONDUCTOR DEVICES
| Title | ΤΕΧΝΟΛΟΓΙΑ ΗΜΙΑΓΩΓΙΚΩΝ ΔΙΑΤΑΞΕΩΝ / TECHNOLOGY OF SEMICONDUCTOR DEVICES |
| Code | ΜΗΦ745 |
| Faculty | Sciences |
| School | Physics |
| Cycle / Level | 2nd / Postgraduate |
| Teaching Period | Winter |
| Coordinator | Charalampos Dimitriadis |
| Common | No |
| Status | Active |
| Course ID | 40002817 |
| Academic Year | 2018 – 2019 |
| Class Period | Winter |
| Faculty Instructors |
|
| Weekly Hours | 2 |
| Class ID | 600133607
|
Course Type 2016-2020
- Scientific Area
Course Type 2011-2015
Specific Foundation / Core
Mode of Delivery
- Face to face
Digital Course Content
- e-Study Guide https://qa.auth.gr/en/class/1/600133607
- At the Website of the School:
Language of Instruction
- Greek (Instruction, Examination)
Learning Outcomes
Basic knowledge required for further studies in the specific field of micro-nano-electronics (PhD thesis).
General Competences
- Apply knowledge in practice
- Retrieve, analyse and synthesise data and information, with the use of necessary technologies
- Adapt to new situations
- Make decisions
- Work autonomously
- Work in teams
- Work in an international context
- Work in an interdisciplinary team
- Generate new research ideas
- Be critical and self-critical
- Advance free, creative and causative thinking
Course Content (Syllabus)
p-n junction: Tecnology of semiconductor devices, energy bands-electrostatic parameters, space charge region in thermal equilibrium and external bias, capacitance of the junction, I-V characteristics under forward and reverse bias.
Transistor MOS: Space charge regions of MOS devices, MOS capacitor, threshold voltage, static characteristics, conductance-transconductance, equivalent circuit, frequency cut-off, effect of substrate bias, fabrication of MOS devices.
Submicron transistor MOS: Experimental transfer and output characteristics, secondary phainomena (channel length modulation, drain induced barrier lowering, effect of geometry on threshold voltage), effect of normal electric field on the mobility, saturation velocity, hot-carrier effects, snapback breakdown, transistor LDD.
CMOS technology: transistor of n-well and p-well, latch-up phenomenon (parasitic bipolar transistor).
Experimental extraction of the parameters of MOSFET: Methodology, experimental application.
FET model for SPICE.
Keywords
p-n junction, transistor MOSFET, secondary phenomena, CMOS, parameters extraction, SPICE models
Educational Material Types
- Notes
- Slide presentations
Course Organization
| Activities | Workload | ECTS | Individual | Teamwork | Erasmus |
|---|---|---|---|---|---|
| Lectures | 26 | 1.0 | ✓ | ||
| Written assigments | ✓ | ||||
| Total | 26 | 1.0 |
Student Assessment
Description
Written exams
Student Assessment methods
- Written Exam with Extended Answer Questions (Summative)
- Written Assignment (Summative)
- Written Exam with Problem Solving (Summative)
Last Update
18-09-2013
