Large-Scale Digital VLSI-ASIC Integrated Circuits
| Title | Ψηφιακά Ολοκληρωμένα Κυκλώματα VLSI-ASIC Μεγάλης Κλίμακας / Large-Scale Digital VLSI-ASIC Integrated Circuits |
| Code | 118 |
| Faculty | Engineering |
| School | Electrical and Computer Engineering |
| Cycle / Level | 1st / Undergraduate |
| Teaching Period | Winter |
| Coordinator | Vasileios Pavlidis |
| Common | No |
| Status | Active |
| Course ID | 600001083 |
Programme of Study: Electrical and Computer Engineering
Registered students: 20
| Orientation | Attendance Type | Semester | Year | ECTS |
|---|---|---|---|---|
| ELECTRICAL ENERGY | Elective Courses | 9 | 5 | 5 |
| ELECTRONICS AND COMPUTER ENGINEERING | Elective Courses | 9 | 5 | 5 |
| TELECOMMUNICATIONS | Elective Courses | 9 | 5 | 5 |
| Academic Year | 2021 – 2022 |
| Class Period | Winter |
| Faculty Instructors | |
| Class ID | 600196728
|
Course Type 2021
Specialization / Direction
Course Type 2016-2020
- Scientific Area
Course Type 2011-2015
Specific Foundation / Core
Mode of Delivery
- Face to face
Digital Course Content
- e-Study Guide https://qa.auth.gr/en/class/1/600196728
- eLearning: https://elearning.auth.gr/course/view.php?id=14134
Language of Instruction
- Greek (Instruction, Examination)
Prerequisites
General Prerequisites
The course units "Low-level HW Digital Systems - Part I and II".
Learning Outcomes
1. Step-by-step learning of a design flow for digital VLSI circuits starting from synthesis all the way to routing and sign-off.
2. Application of concepts and principles for timing analysis of digital VLSI circuits.
3. Learning of design techniques for low-power circuits at multiple layers of the design abstraction.
4. Familiarization with the issue of clock signal distribution and related clock tree synthesis algorithms.
5. Familiarization with the fundamental circuits and design methods of SRAM memory.
General Competences
- Apply knowledge in practice
- Retrieve, analyse and synthesise data and information, with the use of necessary technologies
- Make decisions
- Work autonomously
- Work in teams
- Design and manage projects
- Appreciate diversity and multiculturality
- Respect natural environment
- Demonstrate social, professional and ethical commitment and sensitivity to gender issues
- Be critical and self-critical
- Advance free, creative and causative thinking
Course Content (Syllabus)
The course material is organized in ten sections comprising:
1. Introduction / Definitions / Terminology
2. Design Techniques for Low-Power Digital Circuits
3. Static Timing Analysis (STA)
4. Partition
5. Floorplanning
6. Placement
7. Routing
8. Clock Distribution Networks and Clock Tree Synthesis
9. Design for Testability (DFT)
10. SRAM Memory Design and organization
For each of these sections, examples and related algorithms are presented wherever necessary.
The lab practicals include the use of Cadence IC design tools where the students are required to apply different steps of the design flow to a digital circuit using the provided lab manual.
Keywords
design flow, floorplanning, placement, static timing analysis, lower power consumption, digital integrated circuits
Educational Material Types
- Notes
- Slide presentations
- Video lectures
- Book
Use of Information and Communication Technologies
Use of ICT
- Use of ICT in Course Teaching
- Use of ICT in Communication with Students
- Use of ICT in Student Assessment
Description
Use of the eLearning platform
Course Organization
| Activities | Workload | ECTS | Individual | Teamwork | Erasmus |
|---|---|---|---|---|---|
| Lectures | 59 | 2.0 | |||
| Laboratory Work | 29 | 1.0 | |||
| Tutorial | 29 | 1.0 | |||
| Exams | 33 | 1.1 | |||
| Total | 150 | 5 |
Student Assessment
Description
Written Examination (180 min)
Student Assessment methods
- Written Exam with Multiple Choice Questions (Summative)
- Written Exam with Problem Solving (Summative)
- Report (Summative)
- Labortatory Assignment (Summative)
Bibliography
Course Bibliography (Eudoxus)
Andrew B. Kahng, Jens Lienig, Igor L. Markov, and Jin Hu, "VLSI Physical Design: From Graph Partitioning to Timing Closure," Springer, 2011 (κεφ. 1-5, 7, 8 και διαθέσιμο στον Εύδοξο).
Additional bibliography for study
Hubert Kaeslin, "Top-Down Digital VLSI Design From Architectures to Gate-Level Circuits and FPGAs," Morgan Kaufmann Publishers - Elsevier, 2015 (κεφ. 1, 7).
Bruce Jacob, David Wang, and Spencer Ng, "Memory Systems: Cache, DRAM, Disk," Morgan Kaufmann Publishers, 2007 (κεφ. 5).
Διανέμονται, επίσης, σημειώσεις εν είδη διαφανειών και σχετικών σημειώσεων καθώς και εγχειρίδια για τις εργαστηριακές ασκήσεις.
Last Update
05-09-2021
