Logic Design
| Title | Λογική Σχεδίαση / Logic Design |
| Code | 005 |
| Faculty | Engineering |
| School | Electrical and Computer Engineering |
| Cycle / Level | 1st / Undergraduate |
| Teaching Period | Winter |
| Coordinator | Ioannis Papaefstathiou |
| Common | No |
| Status | Active |
| Course ID | 600000952 |
Programme of Study: Electrical and Computer Engineering
Registered students: 0
| Orientation | Attendance Type | Semester | Year | ECTS |
|---|---|---|---|---|
| CORE | Compulsory Course | 1 | 1 | 5 |
| Academic Year | 2026 – 2027 |
| Class Period | Winter |
| Faculty Instructors | |
| Instructors from Other Categories |
|
| Weekly Hours | 5 |
| Class ID | 600308067
|
Course Type 2016-2020
- Background
Course Type 2011-2015
General Foundation
Mode of Delivery
- Face to face
Digital Course Content
- e-Study Guide https://qa.auth.gr/en/class/1/600308067
- At the Website of the School: http://alexander.ee.auth.gr:8083/eTHMMY/
- eLearning: https://elearning.auth.gr/course/view.php?id=12294
Language of Instruction
- Greek (Instruction, Examination)
Prerequisites
General Prerequisites
1. Fundamentals of secondary school Physics.
2. Basic fundamentals of Electricity and Electronics gained from secondary school.
3. Fundamentals of secondary school Informatics.
Learning Outcomes
1. The understanding of the basic and advanced notions, functions, circuits, units and sys-tems, as they have been described in the "Course Content (Syllabus)" section.
2. The design of typical logic circuits known from the everyday life and the industry, as e.g., digital wrist-watch, alarm-clock radio, the client que priority managing circuit, access con-trol and door entry systems with entry code and alarm, rotation control in electrical machi-nes, addition, multiplication and division circuits for arithmetic calculators, error correcting transmission for satellite and mobile telephony data under thermal and electromagnetic industrial noise.
General Competences
- Apply knowledge in practice
- Retrieve, analyse and synthesise data and information, with the use of necessary technologies
- Make decisions
- Design and manage projects
- Appreciate diversity and multiculturality
- Respect natural environment
- Demonstrate social, professional and ethical commitment and sensitivity to gender issues
- Be critical and self-critical
- Advance free, creative and causative thinking
Course Content (Syllabus)
THEORY:
Radix-Number Systems, conversions between radices, arithmetic operations, negative numbers, error detecting and correcting codes. Boolean Algebra, axioms and theorems, functions and Canonical Forms. Minimization of logic functions, Karnaugh Maps, Quine-McCuskey algorithm. Logic Gates, BUF, NOT, AND, OR, NAND, NOR, EXOR, 3-state gates. Flip Flops, FFs, the SR-, JK-, D- and T-FFs, Master-Slave JK-FF. Timers. Counters, asynchronous and synchronous. Registers, PIPO, SIPO, PISO, SISO, FIFO. Decoders and Encoders. Multiplexers and de-Multiplexers. RAM, ROM/PROM Memories, the basic architecture, read/write signalling, memory registers in computing systems. Arithmetic Circuits, adders, multipliers, the arithmetic-logic unit ALU, number comparator. Arithmetic Computation Graphs ACG and their corresponding circuits. The RTL (Register-Transfer Level) and DSP circuits (Digital Signal Processing - an orientation only approach). BUS architecture, implementation of ACG and Time-Division Multiplexing TDM under BUS concept, estimation of computation's time. Crossbar Architecture. Data Path and Control Path. Basic Computing Machine, Register Bank, Register File, Computing Core, Processor, Controller, Programmable Logic Controller PLC. EXERCISES: 1. Problem solving on classic logic circuit theory (the first part of theory). 2. Design of simple Data Paths and Control Paths. LABORATORY WORKS: 1. Logic gates. 2. Mono-stable and Astable Multi-vibrator based on 555 timer. 3. Flip-Flops and asynchronous counters. 4, 5. Synchronous counters, BCD coder with 7-segment LED display. Multiplexers.
Radix-Number Systems, conversions between radices, arithmetic operations, negative numbers, error detecting and correcting codes. Boolean Algebra, axioms and theorems, functions and Canonical Forms. Minimization of logic functions, Karnaugh Maps, Quine-McCuskey algorithm. Logic Gates, BUF, NOT, AND, OR, NAND, NOR, EXOR, 3-state gates. Flip Flops, FFs, the SR-, JK-, D- and T-FFs, Master-Slave JK-FF. Timers. Counters, asynchronous and synchronous. Registers, PIPO, SIPO, PISO, SISO, FIFO. Decoders and Encoders. Multiplexers and de-Multiplexers. RAM, ROM/PROM Memories, the basic architecture, read/write signalling, memory registers in computing systems. Arithmetic Circuits, adders, multipliers, the arithmetic-logic unit ALU, number comparator. Arithmetic Computation Graphs ACG and their corresponding circuits. The RTL (Register-Transfer Level) and DSP circuits (Digital Signal Processing - an orientation only approach). BUS architecture, implementation of ACG and Time-Division Multiplexing TDM under BUS concept, estimation of computation's time. Crossbar Architecture. Data Path and Control Path. Basic Computing Machine, Register Bank, Register File, Computing Core, Processor, Controller, Programmable Logic Controller PLC. EXERCISES: 1. Problem solving on classic logic circuit theory (the first part of theory). 2. Design of simple Data Paths and Control Paths. LABORATORY WORKS: 1. Logic gates. 2. Mono-stable and Astable Multi-vibrator based on 555 timer. 3. Flip-Flops and asynchronous counters. 4, 5. Synchronous counters, BCD coder with 7-segment LED display. Multiplexers.
Educational Material Types
- Slide presentations
- Book
Use of Information and Communication Technologies
Use of ICT
- Use of ICT in Communication with Students
Course Organization
| Activities | Workload | ECTS | Individual | Teamwork | Erasmus |
|---|---|---|---|---|---|
| Lectures | 31 | 1.0 | |||
| Laboratory Work | 24 | 0.8 | |||
| Tutorial | 31 | 1.0 | |||
| Exams | 64 | 2.1 | |||
| Total | 150 | 5 |
Student Assessment
Description
Written Examination (180 min)
Student Assessment methods
- Written Exam with Problem Solving (Summative)
- Labortatory Assignment (Summative)
Bibliography
Course Bibliography (Eudoxus)
1. Morris Mano, Michael Ciletti "Ψηφιακή Σχεδίαση, 6η Έκδοση: Με Εκτενή Παρουσίαση των Verilog, VHDL και SystemVerilog"
2. Ρουμελιώτης, Σουράβλας, "Ψηφιακή Σχεδίαση, Αρχές και Εφαρμογές", 2η έκδοση, Εκδόσεις Α.Τζιόλα & Υιοί Α.Ε., 2024
Last Update
26-09-2024
