Digital Systems III

Specific Foundation / Core

1. Understanding of the repertoire of problems during the design of extra large computational VLSI-ASIC integrated circuits under low-nanometer technologies (<60 nm); from the beginning of the design up to the dispatch of the design packet to the integrated circuit manufacturer.
2. Theoretic background of the respective methods : analysis and design for low-power/low-energy of digital integrated circuits, fault testing, placement and routing, clock tree synthesis, PVT and MCMM corners, formal verification, logic thresholds and electromagnetic multilayer crosstalk noise estimation, design for manufacturing flow, optical proximity correction, automatic design of processors, instruction set processor ISP. 3. Implementation in practice, by using the respective software, through the design, step-by-step, of a large scale digital VLSI-ASIC integrated circuit (1 million MOSFET / FINFET transistor).

● Power and Energy consumption in digital circuits and systems. Low-Power design. ● Static Timing Analysis, STA ● Fault Testing, methods and techniques, Ad-Hoc, BIST, Boundary Scan and Compressed Scan, Automatic Test Pattern Generation, ATPG. The architecture of Scan Test circuitry and its insertion into the under design configuration. The macro IEEE 11.49.x JTAG testing standard ● Placement and Routing (PnR) on silicon wafer, theory and techniques ● Clock Tree Synthesis, CTS, clock delay, skew and jitter ● Large scale computational VLSI-ASIC Integrated Circuits (hundreds millions of MOSFET transistors) and high-density (<40nm). Package and layout standards, fields and contacts on silicon ● Four design stages ● 1. Initial Synthesis. Mapping, optimization, STA analysis and STA bounds, under SDC (Synopsis Design Constraints), power optimization, Scan Test synthesis, topographical synthesis ● 2. Physical Implementation. PVT (Process Voltage Temperature) analysis, STA corners, MCMM (Multi-Corner Multi-Mode) analysis, Monte Carlo Methods. Floorplanning, DRC (design Rule Check), Placement, CTS synthesis, Routing, Verification ● 3. Signoff Analysis. Formal verification, formal equivalence check, signoff STA with electromagnetic multilayer crosstalk noise estimation, Gate level simulation, signoff power analysis, ATPG ● 4. Design for Manufacturing Flow. Optical errors during lithographical etching in Silicon (< 90 nm). Optical correction (pre-shaping) of masks, OPC (Optical Proximity correction). ● Automatic design of processors (single and multi-core). Instruction Set Processor, ISP. Processor Designer software, advanced design methods, design export to VLSI-ASIC and FPGA-ASIC software.

Large size and low nanometer (<60 nm) digital computational VLSI - ASIC integrated circuits, dynamic power analysis/design, static timing analysis, fault testing, placement and routing, clock tree synthesis, physical implementation, PVT process, static analysis corners, MCMM corners, signoff analysis, formal verification, electromagnetic multilayer crostalk, design for manufacturing flow, optical proximity correction, automatic design of processors, instruction set processor ISP.

16-11-2013